Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
| RXRDYEN | When 1, enables an interrupt when there is a received character available to be read from the RXDATA register. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| TXRDYEN | When 1, enables an interrupt when the TXDATA register is available to take another character to transmit. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| DELTACTSEN | When 1, enables an interrupt when there is a change in the state of the CTS input. |
| TXDISINTEN | When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| OVERRUNEN | When 1, enables an interrupt when an overrun error occurred. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| DELTARXBRKEN | When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted). |
| STARTEN | When 1, enables an interrupt when a received start bit has been detected. |
| FRAMERREN | When 1, enables an interrupt when a framing error has been detected. |
| PARITYERREN | When 1, enables an interrupt when a parity error has been detected. |
| RXNOISEEN | When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 164. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |